1. Field of the Invention
The present invention generally relates to photolithography processes, and more specifically, to a method and system for determining overlay tolerances in photolithographic processes.
2. Prior Art
Photolithography has a broad range of industrial applications, including the manufacture of semiconductors, flat panel displays, micromachines and disk heads. In many of these applications, multiple patterns are formed over, or on top of, one another. For example, generally speaking, integrated circuits may be made by using a series of photolithographic steps to form several layers of patterns on an underlying semiconductor substrate on which the integrated circuit is being made. Each layer may include patterns that are formed on or above patterns of one or more lower layers.
In many cases, patterns must be carefully aligned with lower patterns on the substrate. It is not necessary that these patterns be perfectly aligned, however, and some tolerance is permissible. Determining the proper tolerance between these patterns is an important aspect of the lithographic process. On the one hand, a tolerance that is too low, or tight, may significantly increase the cost and reduce the efficiency of the lithography process without any associated benefit in the performance or quality of the fabricated semiconductor. On the other hand, tolerances that are too high, or loose, may produce degraded product.
Various techniques are known to determine the optimum sizes of the patterns that are formed on the substrate. Process window experiments in photolithography typically consist of focus exposure matrices (which have no direct bearing on yield) or wafer striping; varying image sizes across the wafer to determine the optimum image size, which produces the best yielding chips. Striping provides image size tolerance by printing too large and too small, neither of these procedures consider overlay tolerance.
An object of this invention is to provide a method and system for determining overlay tolerances in photolithography processes.
Another object of the present invention is to provide a tool to determine true overlay tolerance at any image size.
With particular reference to FIG. 1, the present invention involves providing a product wafer, a portion of which is shown in the Figure. A planar insulating layer is deposited on the wafer. The insulating layer may be a chemical-vapor deposited (CVD) silicon oxide and is deposited to a thickness that is typically used on product wafers, such as between 3000 and 8000 Angstroms. Next, a photoresist layer is deposited on the product wafer, and this photoresist layer is then exposed to ultraviolet light through a first reticle. The first reticle is stepped across the wafer, for example by using a step-and-repeat tool, to form a series of images or patterns on the photoresist. This pattern is then transferred into the oxide using an etch process, and the features are filled with a conductive material. More insulator (oxide or low-K dielectric) is coated on the wafer, and the lithographic step begins again using a different reticle with a corresponding pattern. This process is repeated many times and various patterns are positioned over other patterns.
The present invention studies the interaction of image size and feature misalignment. Prior to this invention, the only way to attain this information was to process a large number of lots and to create a trend of image size and alignment vs. yield. The present invention solves the problem by determining the overlay tolerance based on yield data from a single lot. The design can then be altered or the overlay limit can be tightened (or relaxed) based on failure analysis of the regions/features that are most sensitive to misalignment.
Further benefits and advantages of the invention will become apparent from a consideration of the following detailed description, given with reference to the accompanying drawings, which specify and show preferred embodiments of the invention.